# VHDL Code for 2 to 4 decoder

### Binary decoder

### 2 to 4 Decoder design using logic gates

### Truth Table for 2 to 4 Decoder

library IEEE; use IEEE.STD_LOGIC_1164.all;

entity decoder is

port(

a : in STD_LOGIC_VECTOR(1 downto 0);

b : out STD_LOGIC_VECTOR(3 downto 0)

);

end decoder;

architecture bhv of decoder is

begin

process(a)

begin

case a is

when “00” => b <= “0001”; when “01” => b <= “0010”; when “10” => b <= “0100”; when “11” => b <= “1000”;

end case;

end process;

end bhv;

### VHDL Code for 2 to 4 decoder using if else statement

library IEEE; use IEEE.STD_LOGIC_1164.all;

entity decoder1 is

port(

a : in STD_LOGIC_VECTOR(1 downto 0);

b : out STD_LOGIC_VECTOR(3 downto 0)

);

end decoder1;

architecture bhv of decoder1 is

begin

process(a)

begin

if (a=”00″) then

b <= “0001”;

elsif (a=”01″) then

b <= “0010”;

elsif (a=”10″) then

b <= “0100”;

else

b <= “1000”;

end if;

end process;

end bhv;

### VHDL Code for 2 to 4 decoder using logic gates

library IEEE; use IEEE.STD_LOGIC_1164.all;

entity decoder2 is

port(

a : in STD_LOGIC_VECTOR(1 downto 0);

b : out STD_LOGIC_VECTOR(3 downto 0)

);

end decoder2;

architecture bhv of decoder2 is

begin

b(0) <= not a(0) and not a(1);

b(1) <= not a(0) and a(1);

b(2) <= a(0) and not a(1);

b(3) <= a(0) and a(1);

end bhv;